Chip Design for Submicron VLSI: Cmos Laycut and simulatition

Uyemura, John P

Chip Design for Submicron VLSI: Cmos Laycut and simulatition - 1st. - New Delhi Cengage 2011 - xvi, 411p.

RS 380.00

621.395 UYE,J.P

Powered by Koha