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Chip Design for Submicron VLSI: Cmos Laycut and simulatition

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Material type: Text

TextPublication details: New Delhi Cengage 2011Edition: 1stDescription: xvi, 411pDDC classification:

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Holdings
Item type	Current library	Home library	Call number	Status	Notes	Date due	Barcode
Books	School of Electronics Engineering Library	School of Electronics Engineering Library	621.395 UYE,J.P (Browse shelf(Opens below))	Available	08/09/2011		KSEE47770

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Previous	621.395 SAX,P Routing Congestion in VLSI Circuits: Estimation and Optimization	621.395 SIN,A.K Digital VLSI Design	621.395 SUT,S The Verilog P L I Handbook	621.395 UYE,J.P Chip Design for Submicron VLSI: Cmos Laycut and simulatition	621.395 UYE,J.P Introduction to VLSI circuits and Systems	621.395 UYE,JP CMOS Logic Circuit Design	621.395 VAH,F Digital Design	Next

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